Advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometers (nm).
Continuing efforts to achieve higher levels of integration have also led to reductions in the separation distance between adjacent semiconductor features. For example, nanometer processes producing 65 nm and 45 nm gate lengths require a device spacing of, e.g., 120 nm, to achieve reasonable yields within specified process margins. As a result, the number of features that exist on any given semiconductor die is increasing drastically. Obtaining 100% test coverage for each semiconductor feature that exists on each semiconductor die, therefore, is becoming increasingly difficult.
In order to alleviate the amount of test coverage required for any given semiconductor die, statistical methods may be employed to screen the semiconductor die based upon behavior that is statistically deduced from certain parametric data measurements taken on the semiconductor die. One such statistical method implements the so-called “maverick control” methodology to characterize performance of semiconductor devices at wafer sort and/or final test without the need to conduct comprehensive testing on each semiconductor feature. In particular, maverick control limits are utilized to statistically identify those units exhibiting abnormal behavior based on certain parametric data obtained from semiconductor die under test.
Conventional maverick control implementations, however, assume that the probability density function of the critical parametric data relating to any given semiconductor die under test exhibits a normal, or Gaussian, density. Accordingly, semiconductor devices having associated parametric data that lie outside the boundaries of an acceptable normal density, e.g., statistical mean+/−6 standard deviations (6-sigma), may be deemed to be unacceptable.
However, if the probability density function of the critical parametric data relating to any given semiconductor die does not conform to a normal density function, then significant errors are introduced into the statistical method that is used to characterize the semiconductor die under test. As such, yield may be needlessly sacrificed due to a malfunctioning statistical method that incorrectly disposes of semiconductor die that might otherwise be held to be satisfactory and/or fails to identify high-risk die that are ultimately shipped as acceptable units. Furthermore, large amounts of computational resources may be needlessly expended when attempting to adjust the parameters of the malfunctioning statistical method to enhance performance.
Conventional maverick control limit implementations also neglect valuable statistical information that may be ascertained due to their failure to consider the amount of correlation information that may exist between two or more parametric variables. As such, the inability to screen semiconductor die based upon the unknown correlation information further degrades the performance of conventional maverick control limit implementations.
Efforts continue, therefore, to provide a maverick control limit implementation that more accurately reflects the probability density function exhibited by the critical parametric data. Further, efforts continue to develop a maverick control limit implementation that accounts for two highly correlated parametric data variables.